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preliminary data sheet august 2000 trcv012g5 (2.5 gbits/s) and trcv012g7 (2.5 gbits/s and 2.7 gbits/s) limiting amplifier, clock recovery, 1:16 data demultiplexer features n trcv012g5 supports oc-48/stm-16 data rate n trcv012g7 supports: oc-48/stm-16 data rate rs (255, 239) forward error correction (fec) oc-48/stm-16 data rate n fully-integrated limiting amplifier, clock recovery, 1:16 data demultiplexer n no reference clock required for cdr n 2.5 gbits/s data output and 2.5 ghz recovered clock output available for wavelength division multiplex (wdm) or regenerator applications n programmable limiting amplifier offset n programmable data sampling phase n additional cml serial data input for system loopback n parity bit generation n analog and digital loss of signal (los) indicators n optional demultiplexer powerdown mode conserves power n single 3.3 v supply n available in either mbic 025 bicmos technology or lower-power mbic 025 silicon germanium bicmos technology n high-speed lvpecl digital i/o n jitter tolerance, transfer, and generation compliant with the following: telcordia technologies * gr-253 itu-t g.825 itu-t g.958 n loss of signal compliant with the following: telcordia technologies gr-253 * telcordia technologies is a registered trademark of bell com- munications research, inc. applications n sonet/sdh line termination equipment n sonet/sdh add/drop multiplexers n sonet/sdh cross connects n sonet/sdh test equipment description the lucent technologies microelectronics group trcv012g5 operates at the oc-48/stm-16 data rate of 2.5 gbits/s. the trcv012g7 device operates at either 2.5 gbits/s or the rs fec oc-48/stm-16 data rate of 2.7 gbits/s. for clarity, this data sheet refers to the trcv012g5 serial data rate as 2.5 gbits/s and the parallel data and reference clock frequency as 155 mhz. (the precise rates are 2.48832 gbits/s and 155.52 mhz.) when using the trcv012g7 at the fec rate, the 2.5 gbits/s data rate should be interpreted as 2.7 gbits/s and the par- allel and clock frequency should be interpreted as 166 mhz. (the precise rates are 2.66606 gbits/s and 166.62 mhz.) the devices contain a limiting amplifier with 30 db gain, a clock and data recovery pll with high-speed serial clock and data outputs, and a 1:16 demulti- plexer with differential pecl data and clock outputs. the device provides improved optical receiver perfor- mance when used in optically amplified systems due to a direct slice adjust input pin and a 6 ps adjust- ment capability in the slicing decision time. both devices are available in either bicmos or in sige bicmos technology for lower power operation.
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 2 lucent technologies inc. table of contents contents page features ....................................................................................................................... ............................................. 1 applications ................................................................................................................... ............................................ 1 description.................................................................................................................... .............................................1 pin information ................................................................................................................ ..........................................4 functional overview ............................................................................................................ ....................................10 limiting amplifier ............................................................................................................. ........................................10 limiting amplifier operation................................................................................................... ...............................10 clock and data recovery (cdr).................................................................................................. ........................... 11 clock recovery operation ....................................................................................................... .............................11 clock recovery pll loop filter ................................................................................................. .......................... 11 cdr acquisition time........................................................................................................... ................................11 cdr generated jitter ........................................................................................................... ................................11 cdr input jitter tolerance ..................................................................................................... ..............................12 cdr jitter transfer ............................................................................................................ ...................................12 clock recovery jitter tolerance and jitter transfer specifications............................................................. .........13 data path configuration option (endatan) ....................................................................................... ................14 high-speed serial clock and data output enables (enck2g5n, end2g5n)....................................................14 high-speed serial data output mute (mute2g5n) .................................................................................. ..........14 data and cdr configuration options (refseln, inlosn, mutedmxn).........................................................14 decision circuitadjustable sampling time (astref, ast[4:0])................................................................... ......15 loss of signal detection....................................................................................................... ...................................16 digital loss of signal (losdn)................................................................................................. ............................ 16 analog loss of signal (losan, prg_losa) ........................................................................................ ..............16 demultiplexer operation........................................................................................................ ..................................17 parity generation (parityp/n).................................................................................................. .......................... 17 demultiplexer powerdown (pddmxn) ............................................................................................... ..................17 demultiplexer data mute (mutedmxn) ............................................................................................. .................17 ck155p/n low-speed output mute (mute155n)...................................................................................... .........17 cml output structure (used on pins d2g5p/n, ck2g5p/n).......................................................................... .......18 choosing the value of the external cml reference resistors (rref1, rref2) ...............................................18 absolute maximum ratings....................................................................................................... ..............................19 handling precautions ........................................................................................................... ...................................19 operating conditions........................................................................................................... ....................................19 electrical characteristics ..................................................................................................... ....................................20 limiting amplifier specifications .............................................................................................. ............................. 20 optional reference frequency (refclkp/n) specifications ........................................................................ ......20 lvpecl, cmos, cml input and output pins ........................................................................................ ..............21 timing characteristics ......................................................................................................... ....................................23 output timing .................................................................................................................. .....................................23 outline diagram................................................................................................................ .......................................25 128-pin qfp .................................................................................................................... .....................................25 board installation recommendations ............................................................................................. ......................26 thermal considerations (mbic 025 bicmos and mbic 025 sige bicmos) .....................................................26 ordering information........................................................................................................... .....................................27 ds00-234hspl replaces ds00-154hspl to incorporate the following updates.................................................27
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 3 lucent technologies inc. description (continued) additional features include a user-programmable threshold for generating analog loss of signal (los) alarms, a digital los transition detector, an optional reference clock input that can maintain synchronization with no data input signal present, and a loopback data input. to reduce power consumption, the demultiplexer unit, high-speed serial recovered data and clock output, low-speed clock, and low-speed demultiplexer clock output can be inde- pendently powered down in applications where they are not required. the device may be used with the ttrn012g5 or ttrn012g7 transmit synthesizer and multiplexer. 5-8067(f)r.2 note: diagram is representative of device functionality and conceptual signal flow. internal implementation details may be diff erent than shown. figure 1. functional block diagram loss of data d0p d0n d1p d1n d15p d15n parityp ck155p ck155n refclkp refclkn losan limiting data vco 1:16 demultiplexer parity offset cancel end2g5n vthn vthp lainn lainp charge lfp lfn parityn output register losdn inlosn mute155n ck2g5p ck2g5n enck2g5n prg_losa astref resetn to digital logic loss of signal datap datan endatck mutedmxn mutedmx inlos sladj pddmxn pddmx endatan endata refseln mute155 divide d2g5p d2g5n mute2g5 mute2g5n reference ast[4:0] sampler datckp datckn endatckn recovered data vcp vcn rref1 rref2 & slice adjust amplifier 0 1 circuit 1 0 phase/freq. detection pump phase/freq. detection by 16 0 1 0 1 generator 1 0 recovered clock
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 4 lucent technologies inc. pin information 5-8071(f)r.5 figure 2. pin diagram of 128-pin qfp (top view) 1 2 3 5 4 6 7 9 8 18 10 11 13 12 14 15 17 16 19 20 22 21 23 24 26 25 35 27 28 30 29 31 32 34 33 36 37 38 39 41 40 42 43 45 44 54 46 47 49 48 50 51 53 52 55 56 58 57 59 60 62 61 63 64 100 99 98 96 97 95 94 92 93 83 91 90 88 89 87 86 84 85 82 81 79 80 78 77 75 76 66 74 73 71 72 70 69 67 68 65 128 127 126 124 125 123 122 120 121 111 119 118 116 117 115 114 112 113 110 109 107 108 106 105 103 104 102 101 gnd gnd gnd gnd gnd gnd gnd gnd gnd v ccla vthn gnd lainn gnd lainp gnd vthp v ccla sladj prg_losa v ccla v cca v cca gnd gnd vcp lfp lfn vcn gnd nc gnd nc nc v cca v cca v ccd gnd ast0 ast1 ast2 ast3 ast4 d15n gnd gnd gnd d3n d3p v ccd d4n d4p d5n d5p v ccd d6n d6p d7n d7p v ccd d8n d8p d9n d9p gnd d10n d10p v ccd d11n d11p d12n d12p v ccd d13n d13p d14n d14p v ccd d2p d1p d2n d1n v ccd d0n d0p gnd v ccd ck2g5n ck2g5p d2g5n gnd gnd d2g5p v ccd datan v ccd datap datckp datckn v ccd rref1 rref2 astref d15p ck155n ck155p v ccd parityn refclkn v ccd refclkp v ccd mute155n refseln resetn pddmxn mutedmxn mute2g5n losdn losan end2g5n inlosn enck2g5n endatckn nc endatan v ccd parityp
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 5 lucent technologies inc. pin information (continued) note: in table 1, when operating the trcv012g7 device at the oc-48/stm-16 rate, 2.5 gbits/s should be inter- preted as 2.48832 gbits/s. when operating the trcv012g7 device at the rs fec oc-48/stm-16 rate, 2.5 gbits/s should be interpreted as 2.66606 gbits/s. (a similar interpretation should be made for 2.5 ghz.) table 1. pin descriptions2.5 gbits/s and related signals * differential pins are indicated by the p and n suffixes. for nondifferential pins, n at the end of the symbol name designates active-low. ? i = input, o = output. i u = an internal pull-up resistor on this pin, i d = an internal pull-down resistor on this pin, i t = an internal termination resistance of 50 w on this pin. pin symbol * type ? level name/description 30 lainp i analog limiting amplifier inputs (2.5 gbits/s). ac coupling required. 32 lainn 50 d2g5p o cml data output (2.5 gbits/s nrz). 2.5 gbits/s differential data output. n pins are high impedance when end2g5n = 1. n pins are active but forced to differential logic low when mute2g5n = 0. 51 d2g5n 122 end2g5n i u cmos enable d2g5p/n data outputs (active-low). 0 = d2g5p/n buffer enabled 1 or no connection = d2g5p/n buffer powered off 118 mute2g5n i u cmos mute d2g5p/n data output (active-low). 0 = muted 1 or no connection = normal data 53 ck2g5p o cml recovered clock output (2.5 ghz). 2.5 ghz recovered differen- tial clock output. pins are high impedance when enck2g5n = 1. 54 ck2g5n 123 enck2g5n i u cmos enable ck2g5p/n clock output (active-low). 0 = ck2g5p/n buffer enabled 1 or no connection = ck2g5p/n buffer powered off 41 rref1 i analog resistor reference 1. cml current bias reference resistor. (see table 16, page 22 for values.) 40 rref2 i analog resistor reference 2. cml bias reference resistor. place a 1.5 k w resistor to v ccd . 28 vthp i analog voltage threshold adjust input. this input is for monitoring purposes only and should be left open (see figure 3 on page 10). 34 vthn 26 sladj i analog slice level adjustment. adjusts slice level for the limiting amp (see figure 3 on page 10). 119 losan o open drain loss of analog signal (active-low). 25 prg_losa i analog programming voltage for losa threshold. programming voltage is scaled (see figure 7 on page 16). 120 losdn o open drain loss of digital data (active-low). 121 inlosn i u cmos input loss of signal (active-low). forces vco to decrease to its minimum frequency. 0 = force vco low 1 or no connection = normal operation 18 lfp o analog loop filter pll. connect lfp to vcp, and lfn to vcn. 17 lfn 19 vcp i analog vco control. connect vcp to lfp, and vcn to lfn. 16 vcn
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 6 lucent technologies inc. pin information (continued) table 1. pin descriptions2.5 gbits/s and related signals (continued) * differential pins are indicated by the p and n suffixes. for nondifferential pins, n at the end of the symbol name designates active-low. ? i = input, o = output. i u = an internal pull-up resistor on this pin, i d = an internal pull-down resistor on this pin, i t = an internal termination resis- tance of 50 w on this pin. pin symbol * type ? level name/description 43 datckp i t cml clock input for datap/n. buffer is powered down when endatckn = 1. 44 datckn 124 endatckn i u cmos external datckp/n clock select (active-low). selects external datckp/n clock to demultiplexer. 0 = select datckp/n 1 or no connection = select vco clock 46 datap i t cml data input for cml. use this input for system loopback data when lainp/n is used. 47 datan 125 endatan i u cmos enable datap/n inputs (active-low). selects datap/n as data source rather than limiting amplifier output. 0 = select datap/n 1 or no connection = select lainp/n 37 astref i analog adjustable sampling circuit reference resistor. connect a 2.1 k w resistor to v cca . 2ast4i d cmos adjustable sampling time control inputs. ast[4:0] allows introduction of an offset into the sampling time. the most significant bit (a4) is the sign bit and bits a[3:0] represent the magnitude. (see the decision circuit adjustable sampling time (astref, ast[4:0]) section, page 15.) a4 is the polarity bit as follows: 1 = advance 0 = delay sampling point ast[3:0] provides adjustments in steps (increments or decrements) of 6.25 ps in the sampling instant. 3ast3 4ast2 5ast1 6ast0
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 7 lucent technologies inc. pin information (continued) note: in table 2, when operating the trcv012g7 device at the oc-48/stm-16 rate, 155 mbits/s should be inter- preted as 155.52 mbits/s. when operating the trcv012g7 device at the rs fec oc-48/stm-16 rate, 155 mbits/s should be interpreted as 166.62 mbits/s. (a similar interpretation should be made for 155 mhz.) table 2. pin descriptions155.52 mbits/s and related signals * differential pins are indicated by the p and n suffixes. for nondifferential pins, n at the end of the symbol name designates active-low. ? i = input, o = output. i u = an internal pull-up resistor on this pin, i d = an internal pull-down resistor on this pin, i t = an internal termination resistance of 50 w on this pin. pin symbol * type ? level name/description 101 d15p o lvpecl data output (155 mbits/s). 155 mbits/s differential data output. d15 is the most significant bit and is the first received on the lainp/n or datap/n input. when pddmxn = 0, data outputs can be left floating to reduce power consumption. 100 d15n 98 d14p lvpecl 97 d14n 96 d13p lvpecl 95 d13n 93 d12p lvpecl 92 d12n 91 d11p lvpecl 90 d11n 88 d10p lvpecl 87 d10n 85 d9p lvpecl 84 d9n 83 d8p lvpecl 82 d8n 80 d7p lvpecl 79 d7n 78 d6p lvpecl 77 d6n 75 d5p lvpecl 74 d5n 73 d4p lvpecl 72 d4n 70 d3p lvpecl 69 d3n 63 d2p lvpecl 62 d2n 61 d1p lvpecl 60 d1n 58 d0p lvpecl 57 d0n
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 8 lucent technologies inc. pin information (continued) table 2. pin descriptions155.52 mbits/s and related signals (continued) * differential pins are indicated by the p and n suffixes. for nondifferential pins, n at the end of the symbol name designates active-low. ? i = input, o = output. i u = an internal pull-up resistor on this pin, i d = an internal pull-down resistor on this pin, i t = an internal termination resis- tance of 50 w on this pin. pin symbol * type ? level name/description 115 pddmxn i u cmos powerdown demultiplexer circuit (active-low). 0 = demultiplexer powered off, d[15:0]p/n and parityp/n are high-impedance 1 or no connection = demultiplexer powered on 117 mutedmxn i u cmos mute data to demultiplexer circuit (active-low). 0 = mute data 1 or no connection = normal data 108 ck155p o lvpecl recovered clock output (155 mhz). 155 mhz recovered differential clock output. pins are active but forced to differential logic low when mute155n = 0. 107 ck155n 114 mute155n i u cmos mute ck155p/n clock output (active-low). forces ck155p/n to logic low when mute155n is active. 0 = muted 1 or no connection = enabled 105 parityp o lvpecl parity input over data (d[15:0]). active only when pddmxn = 1. 104 parityn 111 refclkp i lvpecl reference clock input (155 mhz). this clock is optional. if applying the refclkp/n, set the refclkp/n to one of the following frequencies: n 155.52 mhz if using the trcv012g5, or the trcv012g7 at the 0c-48/stm-16 rate of 2.48832 ghz. n 166.62 mhz if using the trcv012g7 at the rs fec 0c-48/stm-16 rate of 2.66606 ghz. 110 refclkn 113 refseln i u cmos reference select to pll. selects lainp/n or datap/n, or refclkp/n as the input to the cdr pll. 0 = select refclkp/n 1 or no connection = select lainp/n or datap/n
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 9 lucent technologies inc. pin information (continued) table 3. pin descriptionsglobal signal * differential pins are indicated by the p and n suffixes. for nondifferential pins, n at the end of the symbol name designates active-low. ? i = input, o = output. i u = an internal pull-up resistor on this pin, i d = an internal pull-down resistor on this pin, i t = an internal termination resis- tance of 50 w on this pin. table 4. pin descriptionspower and no-connect signals note: v cca, v ccla, and v ccd have the same dc value, which is represented as v cc unless otherwise specified. however, high-frequency filtering is suggested between the individual supplies. * differential pins are indicated by the p and n suffixes. for nondifferential pins, n at the end of the symbol name designates active-low. ? i = input, o = output. i u = an internal pull-up resistor on this pin, i d = an internal pull-down resistor on this pin, i t = an internal termination resis- tance of 50 w on this pin. pin symbol * type ? level name/description 116 resetn i u cmos reset (active-low). resets all synchronous logic. during a reset, the true data outputs are in the low state and the barred data outputs are in the high state. 0 = reset 1 or no connection = normal operation pin symbol * type ? level name/description 9, 10, 22, 23 v cca ipower analog power supply (3.3 v). 24, 27, 35 v ccla ipower limiting amplifier power supply (3.3 v). 8, 42, 45, 48, 56, 59, 71, 76, 81, 89, 94, 99, 106, 109, 112, 127 v ccd ipower digital power supply (3.3 v). 13, 15, 20, 21 29, 31, 33 1, 7, 36, 38, 39, 49, 52, 55, 6468, 86, 102, 103, 128 gnd i ground ground. 11, 12, 14, 126 nc no connection. these pins must be left open.
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 10 lucent technologies inc. functional overview the lucent technologies microelectronics group trcv012g5 operates at the oc-48/stm-16 data rate of 2.5 gbits/s.* the trcv012g7 device operates at either 2.5 gbits/s or the rs fec oc-48/stm-16 data rate of 2.7 gbits/s. the device performs the data detection, clock recovery, and 1:16 demultiplexing operations required to support 2.5 gbits/s applications compliant with telcordia technologies and itu standards. a differential limiting amplifier with an adjustable threshold amplifies the 2.5 gbits/s serial data waveform from an off-chip transimped- ance amplifier (tia). alternatively, a cml logic level input can be selected as the data source. a pll recovers the clock which is used to retime the data. the decision sampling phase can be adjusted for optimal system perfor- mance. the 2.5 gbits/s serial data and the 2.5 ghz recovered clock signal are available at cml outputs, or alter- natively, they can be disabled or the data can be muted. a 1:16 data demultiplexer performs the serial-to-parallel conversion and generates 16 parallel outputs at a 155 mbits/s rate as well as a parity indicator. the parallel output data is aligned to a 155 mhz clock derived from the 2.5 ghz recovered clock. loss of analog signal (losa) and loss of digital transitions (losd) are indicated. a 155 mhz reference clock may optionally be applied to serve as a frequency reference when data timing is lost. limiting amplifier limiting amplifier operation the limiting amplifier receives the input serial 2.5 gbits/s data waveform from a transimpedance amplifier interface. the limiting amplifier inputs are internally terminated with 50 w resistors to ensure high input return loss perfor- mance. the signal is amplified with a small signal gain of approximately 30 db to a saturation level of approxi- mately 800 mvp-p in order to provide a digital waveform to the clock and data recovery pll. full limiting is guaranteed for inputs of 15 mvp-p or greater on each input rail (30 mvp-p differential). if the input signal level is below a user-configurable threshold for a sufficiently long period of time, the losa signal is asserted. (for more detail on the losa functions, see the analog loss of signal (losan, prg_losa) section on page 16.) a typical interface between the lightwave receiver and the limiting amplifier is shown in figure 3. note: it is recommended to use a differential interface from the lightwave receiver device with ac coupling. the slicing level can be adjusted by varying the voltage on the sladj pin within 300 mv of v cc /2. this feature can be used to improve ber performance in optical receivers and optical amplifier systems. the relationship between the external voltage and the slicing level is given in table 9 on page 20. if the voltage at this pin is tied below 0.5 v, the external slice adjustment is disabled and only the internal offset cancellation feature is active. the user should connect the sladj pin to gnd if the slice adjust feature is not needed. the limiting amplifier will per- form in accordance with the specifications shown in table 9. 5-8068(f) figure 3. typical tia to limiting amplifier interface * the oc-48/stm-16 data rate of 2.48832 gbits/s is typically approximated as 2.5 gbits/s in this document when referring to the application rate. the rs fec oc-48/stm-16 data rate is 2.66606 gbits/s and is approximated as 2.7 gbits/s in this document. similarly, the oc-3/ stm-1 data rate of 155.52 mbits/s is typically approximated as 155 mbits/s, and the rs fec oc-3/stm-1 data rate of 166.62 mbits /s is approximated as 166 mbits/s. the exact frequencies are used only when necessary for clarity. limiting offset cancel vthn vthp lainn lainp tia lightwave receiver 50 w 50 w 0.047 m f 0.047 m f 0.1 m f 0.1 m f sladj & slice adjust amplifier device
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 11 lucent technologies inc. clock and data recovery (cdr) clock recovery operation the cdr circuit uses a pll to extract the clock and retime the 2.5 gbits/s data. the 2.5 gbits/s data and the 2.5 ghz recovered clock are available as outputs, as well as a 155 mhz clock derived from the recovered clock. clock recovery pll loop filter a typical loop filter that meets the oc-48 jitter transfer template is shown in figure 4. connect the filter compo- nents and also connect lfp to vcp and connect lfn to vcn. the component values can be varied to adjust the loop dynamic response (see table 5). table 5. clock recovery loop filter component values * capacitor c1 should be either ceramic or nonpolar. 5-8061(f).a figure 4. clock recovery pll loop filter components cdr acquisition time the limiting amplifier plus cdr will acquire phase/frequency lock within 10 ms after powerup and a valid sonet signal or a 2 23 C 1 prbs data signal is applied. cdr generated jitter the limiting amplifier plus cdrs generated jitter performance meets the requirements shown in table 6. these specifications apply to the jitter generated at the 2.5 gbits/s recovered clock pins (ck2g5p/n) when the following occur: no jitter is present on the input, the limiting amplifiers input signal is within the valid level range given in table 9 on page 20, and the data sequence is a valid oc-48 sonet/sdh signal. table 6. clock and data recovery generated jitter specifications * this denotes the device specification for system sonet/sdh compliance when the loop filter in table 5 and figure 4 is used. components values for 2 mhz loop bandwidth c1* 0.47 m f 10% c2, c3 10 pf 20% r1 82.5 w 5% r2 100 k w 5% parameter typical max (device) * unit generated jitter (p-p): measured with 12 khz to 20 mhz bandpass filter 0.06 0.10 uip-p generated jitter (rms): measured with 12 khz to 20 mhz bandpass filter 0.008 0.01 uirms c 3 c 2 c 1 r 1 lfn/vcn lfp/vcp r 2
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 12 lucent technologies inc. clock and data recovery (cdr) (continued) cdr input jitter tolerance the limiting amplifier plus cdrs jitter tolerance performance meets the requirement shown in figure 5 on page 13 when the limiting amplifiers input signal is within the valid level range given in table 9 on page 20, the loop filter in figure 4 is used, and the data sequence is a valid oc-48 sonet/sdh signal. cdr jitter transfer using the loop filter in figure 4, the cdrs jitter transfer performance meets the requirement shown in figure 6 when the input jitter magnitude is within the jitter tolerance requirements given in figure 5 and the data sequence is a valid oc-48 sonet/sdh signal. this specification applies to the jitter transferred from the limiting amplifiers input to the 2.5 gbits/s recovered clock pins (ck2g5p/n).
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 13 lucent technologies inc. clock and data recovery (cdr) (continued) clock recovery jitter tolerance and jitter transfer specifications 5-8069(f)r.1 figure 5. receiver jitter tolerance 5-8062(f)r.2 figure 6. receiver jitter transfer 0.01 ui 0.1 ui 1 ui 10 ui 100 1k 10k 100k 10 frequency (hz) 1m 100 ui 10m (6 khz, 1.5 uip-p) (100 khz, 1.5 uip-p) (600 hz, 15 uip-p) (1 mhz, 0.15 uip-p) (10 hz, 15 uip-p) 60 40 20 0 1k 10k 100k 1m 10m 50 30 10 100m frequency (hz) jitter out/jitter in (db) (2 mhz, 0.1 db)
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 14 lucent technologies inc. clock and data recovery (cdr) (continued) data path configuration option (endatan) either the limiting amplifier (lainp/n) or a cml logic level input (datap/n) can be selected as the source of the 2.5 gbits/s data signal. the datap/n input can be used if the limiting amplifier is not needed, or it can be used as a system loopback path when the limiting amplifier is the normal data path. if the limiting amplifier is not used in normal operation, the lainp/n pins should be grounded through a series ac coupling of 0.1 m f. high-speed serial clock and data output enables (enck2g5n, end2g5n) separate output enables are provided for the 2.5 ghz recovered clock output (ck2g5p/n) and the 2.5 gbits/s data output (d2g5p/n). these enables are active-low cmos inputs with internal pull-up resistors. a ground or logic low applied to the pin enables the corresponding output. when disabled, the pins should be either left floating, or be connected to a load which returns to v cc . the high-speed serial clock and data outputs must not be con- nected directly to ground when they are disabled. high-speed serial data output mute (mute2g5n) the 2.5 gbits/s data output (d2g5p/n) may be forced to a logic-low state using mute2g5n. this may be desir- able if the quality of the input data is suspect, as may be the case under losa or losd conditions. mute2g5n is an active-low cmos input. data and cdr configuration options (refseln, inlosn, mutedmxn) a 155 mhz clock (refclkp/n) may optionally be provided as a frequency reference to the clock recovery pll in order to control the recovered clock frequency when data timing is lost, as may be the case under losa or losd conditions. if refclkp/n is provided, refseln can be used to select refclkp/n as the frequency reference to the clock recovery pll. the inlosn pin will force the vco to decrease to its minimum frequency. this will prevent the vco frequency from drifting to a high value during invalid signal conditions. inlosn may be used to limit the recovered clock fre- quency in systems that do not provide a refclkp/n signal. the mutedmxn pin will force logic-low data into the demultiplexer, and therefore, keep all demultiplexer outputs in the logic-low state. mutedmxn will not affect the operation of the cdr circuits. this may be desirable if the quality of the input data is suspect as may be the case under losa or losd conditions. the user may utilize the refseln, inlosn, and mutedmxn pins in any combination to achieve the desired response under los conditions.
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 15 lucent technologies inc. decision circuitadjustable sampling time (astref, ast[4:0]) the adjustable sampling time (ast) feature allows a deliberate time offset to be introduced for the data recovery sampling instant relative to the recovered clock. the sampling instant is normally set by the clock recovery phase- locked loop (pll) to be midway between the mean values of adjacent nrz data polarity transitions, which pro- vides an ideal setup and hold time margin of one half the data period. by setting the ast[4:0] control bits, the user may shift the instant at which the plls recovered clock samples the receive data eye. the ast[4] bit acts as a polarity setting, ast[3] represents the most significant magnitude bit, and ast[0] represents the least significant magnitude bit. since this results in two decoded zero time offset states, ast[4:0] = 00000 is used to disable the sampling offset feature entirely and will result in traditionally defined midpoint sampling, whereas ast[4:0] = 10000 will also result in midpoint sampling by using the ast feature in its zero time offset condition. with ast[4] set to a logic high, increasing the ast[3:0] hexadecimal code causes the sampling point to monotonically advance in time; with ast[4] set to a logic low, the sample time is delayed more as ast[3:0] increases. the astref pin should be tied to the positive power supply through a low-capacitance 1%, 2.1 k w resistor. this provides a stable reference resistor to the ast circuitry . the ast control bit configurations and corresponding offset times are shown in table 7 . table 7. adjustable sampling time (ast) control code note: when operating the trcv012g7 at the fec rate, the 6.25 ps step should be scaled down by 7%. ast[4:0] time offset (ps) ast[4:0] time offset (ps) 01111 C93.75 10000 0.00 01110 C87.50 10001 6.25 01101 C81.25 10010 12.50 01100 C75.00 10011 18.75 01011 C68.75 10100 25.00 01010 C62.50 10101 31.25 01001 C56.25 10110 37.50 01000 C50.00 10111 43.75 00111 C43.75 11000 50.00 00110 C37.50 11001 56.25 00101 C31.25 11010 62.50 00100 C25.00 11011 68.75 00011 C18.75 11100 75.00 00010 C12.50 11101 81.25 00001 C6.25 11110 87.50 00000 0.00 11111 93.75
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 16 lucent technologies inc. loss of signal detection the loss of signal circuits are used to detect the conditions of low input signal level or no data transitions at the input. the losdn and losan signals can be processed and/or filtered to meet various system-dependent requirements on declaring loss of signal. digital loss of signal (losdn) the losdn signal alarm is set when no transitions appear in the data path for more than 2.3 m s. the losdn sig- nal will become active before 100 m s of no transitions has occurred. when ac coupling the 2.5 gbits/s data to the high gain limiting amplifier, in the presence of no significant amplitude data transitions, noise at the limiting ampli- fiers input may be amplified and appear to be a data transition. this may change the state of losdn. analog loss of signal (losan, prg_losa) low signal levels are detected by the limiting amplifier with an optional user-programmable analog loss of signal (losa) threshold. as shown in figure 7, applying a voltage to the prg_losa pin will adjust the losa trip point. when the voltage on prg_losa is 0 v, losan will never be active even if the level at the limiting amplifier input is zero. when the voltage on prg_losa is greater than approximately 1 v and less than 2 v, losan will always be active regardless of the signal level at the limiting amplifier input. if the voltage of the prg_losa pin exceeds 2 v, the threshold defaults to approximately 12 mvp-p differential. this voltage can be adjusted while monitoring the ber of the system, and is typically set to activate losan for input levels corresponding to a ber of just above 10 C3 . losan will not be asserted unless the alarm condition exists for at least 2.3 m s. the losan pin will be de- asserted when the input level becomes greater than the losa threshold by an amount corresponding to 1 db (typ- ical) optical power input. the input resistance of the prg_losa pin is typically 50 k w , so a resistor voltage divider between v cc and ground may be used to set the prg_losa level if the v cc tolerance and variability is adequate. 5-8070(f)r.2 figure 7. typical losa threshold vs. prg_losa voltage vs. data pattern 45 40 35 30 25 20 15 10 5 0 0.0 0.5 0.1 0.2 0.3 0.4 0.6 0.7 0.8 0.9 1.0 program voltage v in (mvp-p) at which losa activates data pattern 1/1 prbs 8/8
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 17 lucent technologies inc. demultiplexer operation the serial 2.5 gbits/s data is clocked into a 1:16 demultiplexer by the recovered 2.5 ghz clock. the demultiplexed parallel data is retimed with a 155 mhz clock that is derived from the recovered clock. the relationship between the serial input data and the parallel d[15:0] bits is given in figure 8. d15 is the bit that was received first in time in the serial input data stream. 5-8063(f).a figure 8. serial input to parallel output data relationship parity generation (parityp/n) the parity pin (parityp/n) is a logic 0 when the number of 1s in the 16-bit output register is an even number, and the parity pin is a logic 1 when the number of 1s in the output register is an odd number. demultiplexer powerdown (pddmxn) the entire demultiplexer and parity generator functionality can be powered down for systems requiring only the 2.5 ghz clock and data outputs. setting pddmxn = 0 powers down the demultiplexer and parity generation func- tions as well as the ck155p/n output clock signal. when pddmxn = 0, the d[15:0] and parityp/n pins should be left unconnected. demultiplexer data mute (mutedmxn) setting the mutedmxn = 0 mutes the data going into the demultiplexer and forces all zeros to appear at the par- allel outputs (d[15:0]). ck155p/n low-speed output mute (mute155n) the 155 mhz low-speed clock output (ck155p, ck155n) can be forced to logic low by setting mute155n, which is an active-low cmos input with an internal pull-up resistor. a ground or logic low applied to mute155n mutes the ck155p/n output. d15 d14 d1 d0 d15 time (d15 received first) (d0 received last) (msb) (lsb)
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 18 lucent technologies inc. cml output structure (used on pins d2g5p/n, ck2g5p/n) the cml architecture is essentially a current-steering mechanism combined with an amplifier. this makes the out- put swing of the signal a function of the termination resistor and the programmable output current. the user should connect external termination resistors from the cml output pins to v cc . the on-chip, 100 w pull-up resistors pro- vide a dc path when using an ac-coupled load. the voltage swing of a cml signal is typically 400 mv, half that of ecl/pecl. the lower pulse amplitude reduces noise transients, crosstalk, and emi. it also uses half the amount of current through the termination resistors. the schematic of a typical cml output structure is shown in figure 9. 5-8065(f)r.2 figure 9. typical cml output structure choosing the value of the external cml reference resistors (rref1, rref2) the flexibility of the cml interface permits certain parameters to be customized for a particular application. the rref1 resistor controls the cml output driver current source. adjusting this tail current and termination resistors will allow signal amplitude control (see the cml output specifications for limitations, page 22 and page 24) and flexibility in termination schemes. with rref2 set to 1.5 k w , the equation for the cml output current is the following: iout = (18)*(1.21)/rref1 the cml outputs have on-chip 100 w load resistors to v cc in order to accommodate capacitive ac coupling. with a 50 w 1% load, the effective load resistance will be 33.33 w 6%. for a 400 mv voltage swing into the 50 w load, set rref1 to 1.8 k w . for a 600 mv voltage swing, set rref1 to 1.2 k w . in both cases, rref2 remains fixed at a value of 1.5 k w. device-internal cml output buffer circuit external output termination v cc v cc 50 w 50 w v cc v cc 100 w 100 w vref 18x v cc rref1 rref2 + C i out i out
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 19 lucent technologies inc. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in the defined model. no industrywide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes: operating conditions table 8. recommended operating conditions parameter min max unit power supply voltage (v cc ) 4.0 v storage temperature C40 125 c pin voltage gnd C 0.5 v cc + 0.5 v device voltage trcv012g5 3 200 v trcv012g7 3 200 v parameter symbol min typ max unit power supply (dc voltage) 3.135 3.3 3.465 v ground v input voltage: low high v il v ih (see table 11, table 13, table 15.) (see table 11, table 13, ta b l e 1 5 . ) (see table 11, table 13, ta b l e 1 5 . ) v v temperature: ambient junction t a C40 85 c 0 125c power dissipation: mbic 025 bicmos mbic 025 sige bicmos p d p d 2.5 1.45 3.43 1.73 w w
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 20 lucent technologies inc. electrical characteristics limiting amplifier specifications table 9. limiting amplifier characteristics optional reference frequency (refclkp/n) specifications the cdr operates without any reference clock. however, a reference clock input is available should the user want to maintain the cdr frequency lock without any data input. n when using the trcv012g5 device, a 155.52 mhz differential lvpecl clock can be applied to the refclkp/n input. n when using the trcv012g7 device at the oc-48/stm-16 rate, a 155.52 mhz differential lvpecl clock can be applied to the refclkp/n input. n when using the trcv012g7 device at the rs fec oc-48/stm-16 rate, a 166.62 mhz differential lvpecl clock can be applied to the refclkp/n input. table 10 provides the characteristics of the refclkp/n input. table 10. reference frequency characteristics * includes effects of power supply variation, temperature, electrical loading, and aging. the 20 ppm tolerance is required to meet sonet/sdh requirements if the reference frequency is used for system clocking when timing recovery is lost. ? specified range is to be compatible with environmental specification of trcv012g5 or trcv012g7. applications requiring a reduced temperature range may specify the reference frequency oscillator accordingly. parameter min typical max unit data input level for full amplifier limiting (differential input) 30 1200 mvp-p small-signal gain 26 30 32 db small-signal bandwidth 3 ghz input referred wideband noise (dc2.5 ghz) 170 m vrms input return loss (lainp/lainn pins): 100 mhz2 ghz 2 ghz3 ghz C20 C15 db db input slice level adjustment 0.01*(sladj C v cc /2) v sladj input range v cc /2 C 0.3 v cc /2 + 0.3 v slice feature disable voltage (sladj) 0.5 v parameter min typ max unit reference frequency (refclkp/n) 155.52 mhz 166.62 mhz reference frequency tolerance* C20 20 ppm duty cycle 40 60 % temperature ? C40 85 c supply voltage ? 3.10 3.60 v
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 21 lucent technologies inc. electrical characteristics (continued) lvpecl, cmos, cml input and output pins notes: 1. for table 11 through table 18, v cc = 3.3 v 5%, t a = C40 c to +85 c; these tables apply to both mbic 025 bicmos and mbic 025 sige bicmos technologies. 2. for more information on interpreting cml specifications, see the cml output structure (used on pins d2g5p/n, ck2g5p/n) section on page 18. table 11. lvpecl input pin characteristics table 12. lvpecl output pin characteristics table 13. cmos input pin characteristics table 14. open drain output pin characteristics applicable pins symbol parameter conditions min typ max unit refclkp/n v ih input voltage high referred to v cc C1165 C880 mv v il input voltage low referred to v cc C1810 C1475 mv i ih input current high leakage v in = v ih (max) 20 m a i il input current low leakage v in = v il (min) 5 m a applicable pins symbol parameter conditions min typ max unit d[15:0]p/n, parityp/n, ck155p/n v oh output voltage high load = 50 w connected to v cc C 2.0 v v cc C 1.31 v cc C 1.20 v cc C 0.90 v v ol output voltage low load = 50 w connected to v cc C 2.0 v v cc C 1.95 v cc C 1.88 v cc C 1.80 v applicable pins symbol parameter conditions min max unit end2g5n, enck2g5n, resetn, endatan, endatckn, refseln, mutedmxn, pddmxn, mute155n, mute2g5n v ih input voltage high v cc C 1.0 v cc v v il input voltage low gnd 1.0 v i ih input current high leakage v in = v cc 10 m a i il input current low leakage v in = gnd C225 m a ast[4:0] i ih input current high leakage v in = v cc 225 m a i il input current low leakage v in = gnd C10 m a applicable pins symbol parameter conditions min max unit losan, losdn v oh output voltage high r l 3 5 k w v cc C 0.5 v cc v v ol output voltage low r l 3 5 k w gnd 0.5 v c l output load capacitance 30 pf
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 22 lucent technologies inc. electrical characteristics (continued) lvpecl, cmos, cml input and output pins (continued) table 15. cml input pin dc characteristics table 16. cml output pin dc characteristics * applies when rref1 = 1 k w. ? applies when rref1 = 1.8 k w. ? applies when rref1 = 6 k w. applicable pins symbol parameter conditions min typ max unit datap/n, datckp/n v il input voltage low v cc C 0.4 v v ih input voltage high v cc v applicable pins symbol parameter conditions min * typ ? max ? unit d2g5p/n, ck2g5p/n v ol output voltage low rref2 = 1.5 k w r l = 50 w all signals differential v cc C 1.2 v cc C 0.4 v v oh output voltage high v cc v cc + 0.3 v i ol output current low 3.6 12 18 ma i oh output current high 0 1 m a
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 23 lucent technologies inc. timing characteristics output timing the timing relationships between the 155 mhz or 166 mhz output clock (ck155p/n) and the output demultiplexer data (d[15:0]p/n) and the output parity (parityp/n) are shown in figure 10. 5-7726(f).fr.4 figure 10. transmit timing waveform with 155 mhz or 166 mhz clock the 155 mhz or 166 mhz output clock and data signals from figure 10 are characterized in table 17. table 17. lvpecl output pin ac timing characteristics applicable pins symbol parameter conditions min typ max unit ck155p/n duty cycle all signals differential 48 50 52 % t period 155.52 mhz clock period 6.43 ns 166.62 mhz clock period 6.00 ns d[15:0]p/n, parityp/n, ck155p/n t dd1 time delay from clock edge to d[15:0]p/n edge 2.9 3.2 3.9 ns t dd2 time delay from clock edge to parityp/n edge 3.3 4.0 4.7 ns t rise , t fall rise, fall times: 20%80% 200 500 800 ps t skew transition skew rise to fall C100 0 100 ps output ck155p ck155n outputs d[15:0]p/n data 1 t period data 2 data 3 parity 1 parity 2 parity 3 parityp/n t dd2 t dd1
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 24 lucent technologies inc. timing characteristics (continued) output timing (continued) the timing relationship between the 2.5 ghz or 2.7 ghz output clock (ck2g5p/n) and the 2.5 gbits/s or 2.7 gbits/s output data (d2g5p/n) is shown in figure 11. 5-7726(f).er.4 figure 11. transmit timing waveform with 2.5 ghz or 2.7 ghz clock the 2.5 ghz or 2.7 ghz output clock and data signals from figure 11 are characterized in table 18. table 18. cml output pin ac timing characteristics applicable pins symbol parameter conditions min typ max unit ck2g5p/n duty cycle rref1 = 1.8 k w rref2 = 1.5 k w r l = 50 w all signals differential 40 50 60 % t period 2.48832 ghz clock period 402 ps 2.66606 ghz clock period 375 ps d2g5p/n, ck2g5p/n t dd time delay from clock edge to d2g5p/n edge 151 201 251 ps t rise , t fall rise, fall times: 20%80% 50 80 120 ps t skew transition skew rise to fall C10 0 10 ps output ck2g5p ck2g5n output d2g5p/n data 1 t period data 2 data 3 t dd
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 25 lucent technologies inc. outline diagram 128-pin qfp dimensions are in millimeters. 5-8416(f)r.2 3.30 (ref) 0.50 (typ) 2.80 (ref) 1 38 65 102 103 128 17.20 0.20 19.86 0.10 64 39 1 lucent code name yywwl xxxxxknv 0.38 (ref) detail a 11.43 0.18 23.20 0.20 13.89 0.10 8.13 (ref) 2.89 (ref) 17.52 0.18 8.13 (ref) 0.20 0.06 0.000 to 0.100 8.13 (ref) 2.89 (ref) (8.13) 2 x 0.305 heat sink 5.87 (ref) 0.800 0.150 1.600 0.150 detail a
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 26 lucent technologies inc. outline diagram (continued) board installation recommendations 5-9862 (f)r.1 figure 12. heat sink ground pattern thermal considerations (mbic 025 bicmos and mbic 025 sige bicmos) the trcv012g5 and trcv012g7 devices use a square heat sink on the bottom of the package for heat dissipa- tion. this heat sink is planar with the lead surface which contacts the board. for optimum heat transfer, the heat sink should be soldered to the application board using the suggested footprint shown above. depending on the application more heat sinking may be required. note: certain precautions must be taken when using solder. for installation using a constant temperature solder, temperatures of under 300 c may be employed for periods of time up to 5 seconds, maximum. for installa- tion with a soldering iron (battery operated or non-switching only), the soldering tip temperature should not be greater than 300 c and the soldering time for each lead must not exceed 5 seconds. table 19. thermal resistance parameter symbol conditions unit (c/w) thermal resistance, junction to board q jb no air flow, device soldered to board 11.5 thermal resistance, junction to ambient q ja 100 lfpm, device soldered to board 18 300 lfpm, device soldered to board 15.6 500 lfpm, device soldered to board 14.6 0.705 0.193 0.100 0.012 0.060 0.100 0.311 0.941 0.320 0.050 0.160 0.160 0.270 0.270 0.050 heat sink typ ?0.032 0.320 ground pattern 0.019685
preliminary data sheet trcv012g5 and trcv012g7 august 2000 limiting amplifier, clock recovery, 1:16 data demultiplexer 27 lucent technologies inc. ordering information ds00-234hspl replaces ds00-154hspl to incorporate the following updates 1. added a second technology, mbic 025 sige bicmos, to the data sheet. 2. page 8, refclkp/n pins, corrected definition. 3. page 11, table 5, updated c1, r1, and r2 values in clock recovery loop filter component values. 4. page 19, absolute maximum ratings, added maximum power supply value of 4.0 v. 5. page 19, handling precautions, corrected esd threshold value from tbd to 3 200 v. 6. page 19, table 8, corrected bicmos power dissipation from tbd to 3.43 w in recommended operating con- ditions; added mbic 025 sige bicmos power dissipation values. 7. page 19, table 8, added junction temperature in recommended operating conditions. 8. page 21, table 12, corrected values in lvpecl output pin characteristics. 9. page 23, table 17, updated minimum duty cycle from 40% to 48%, maximum duty cycle from 60% to 52%, and tdd1 minimum value from 2.5 ns to 2.9 ns in lvpecl output pin ac timing characteristics. 10. page 26, added the section board installation recommendations and thermal considerations (mbic 025 bicmos and mbic 025 sige bicmos). 11. page 27, ordering information, added mbic 025 sige bicmos comcodes. device code package temperature comcode (ordering number) trcv012g5: trcv012g5 (bicmos) trcv012g53xe1 (sige bicmos) 128-pin qfp 128-pin qfp C40 c to +85 c C40 c to +85 c 108419953 108700675 trcv012g7: trcv012g7 (bicmos) TRCV012G73XE1 (sige bicmos) 128-pin qfp 128-pin qfp C40 c to +85 c C40 c to +85 c 108560343 108700683
trcv012g5 and trcv012g7 preliminary data sheet limiting amplifier, clock recovery, 1:16 data demultiplexer august 2000 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 2000 lucent technologies inc. all rights reserved august 2000 ds00-234hspl (replaces ds00-154hspl) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)

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